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3D-optimized SRAM macro design and application to memory-on-logic 3D-IC at advanced nodes

par Chen, Rongmei;Weckx, Pieter;Salahuddin, Shairfe Muhammad;Kim, Soon-wook;Sisto, Giuliano ;Van Der Plas, Geert;Stucchi, Michele;Baert, Rogier;Debacker, Peter;Na, Myung-hee;Ryckaert, Julien;Milojevic, Dragomir ;Beyne, Eric
Référence Technical Digest - International Electron Devices Meeting, IEDM, 2020-December, page (15.2.1-15.2.4), 9371905
Publication Publié, 2020-12-01

Article révisé par les pairs

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Résumé :

We present local global SRAM macro optimizations for 3nm FinFET and 2nm Nanosheet using Face-to-Face (F2F) and Wafer-to-Wafer (W2W) hybrid bonding at sub 1um pitch. Bonding pad parasitics are measured experimentally to calibrate RC models of the pad used to evaluate 3D-optimized memory macro delays. 3Doptimized macros are designed to reduce the macro external delay by ~50%. With customized SRAM BEOL, performance improvement of up to 70% for larger memories is observed compared with 2D macro. We also show that bit-cell tech-level optimizations have minor impact on the performance of large caches at advanced nodes due to high metal resistance in the macro global routing. Finally, at system-level we partition a L2 data memory (with 3D-optimized macro) from logic showing that the 3D implementation achieves a total of 33% performance gain with respect to a 2D implementation.