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Enhancing Multi-Core SoC Performance through AuC Integration for Advanced 3D-IC Systems

par Bilgic, Refik;Das, Sudipta;Kumari, Bhawana;Ryckaert, Julien;Biswas, Dwaipayan;Milojevic, Dragomir
Référence I E E E Embedded Systems Letters
Publication Publié, 2026-04-09

Article révisé par les pairs

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Résumé :

This paper explores the application of Array-Under-CMOS (AuC) technology for the cache hierarchy in a commercial 4-core mobile System-on-Chip (SoC). This study evaluates the impact of AuC integration on Power, Performance & Area (PPA) metrics for L1, L2 caches at SoC level. We evaluated memory partitioning not only in comparison to the 2D baseline, but also in relation to the 3D Memory-on-Logic (MoL) integration. Our findings indicate that AuC technology can boost the SoC frequency of up to 71% and achieve 56% higher CPU efficiency compared to traditional 2D implementations. Furthermore, the study highlights the advantages of heterogeneous integration, where SRAM bit-cells are in the N3 FinFET (N3-FF) technology and the periphery in the A10 Nanosheet (A10-NS) technology, resulting in 12% power savings and 18% better CPU efficiency compared to baseline 2D. These results demonstrate the potential of AuC technology to optimize the design of SRAM, contributing to the overall efficiency of computing systems by addressing the memory bottleneck.