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Design and Sign-off Methodologies for Wafer-To-Wafer Bonded 3D-ICs at Advanced Nodes (invited)

par Sisto, Giuliano ;Chen, Rongmei;Chou, Richard;Van Der Plas, Geert;Beyne, Eric;Metcalfe, Rod;Milojevic, Dragomir
Référence International Workshop on System Level Interconnect Prediction, SLIP, 2021-November, page (17-23)
Publication Publié, 2021-11-01

Article révisé par les pairs

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Résumé :

In this paper, we describe different design methodologies to bridge the gap between 3D and 2D Integrated Circuits in the Electronic Design Automation framework. An extended version of a Die-by-Die place and route flow for 3D systems is presented, focusing on the power management and timing optimization aspects. The corresponding sign-off methodologies to perform 3D power and timing optimization are developed using commercial tools. For both 3D-aware Multi-Die rail analysis and Static Timing Analysis, sample results on a test design example are included as means to validate the flows.