par Beyne, Eric;Milojevic, Dragomir 
;Van Der Plas, Geert;Beyer, Gerald
Référence Technical Digest - International Electron Devices Meeting, IEDM, 2021-December, page (3.6.1-3.6.4)
Publication Publié, 2021-11-01
;Van Der Plas, Geert;Beyer, GeraldRéférence Technical Digest - International Electron Devices Meeting, IEDM, 2021-December, page (3.6.1-3.6.4)
Publication Publié, 2021-11-01
Article révisé par les pairs
| Résumé : | 2.5D 'Chiplet' approaches allow for a dense integration of independently designed fabricated ICs. However, this inherently adds a significant interconnect latency, therefore limiting the application to latency-tolerant applications. This added latency can be eliminated by introducing a '3D-SoC' design approach. This is an extension of the highly successful 2D System-on-Chip (SoC) design methodology, where the system is automatically partitioned into separate chips that are concurrently designed interconnected in the 3rd dimension. To realize such 3D-SoC circuits, the 3D interconnect pitch needs to be scaled further beyond the current state-of-the-art. Our current research has demonstrated the feasibility of realizing such interconnections at 7µm pitch for die-to-die stacking and 700nm pitch for wafer-to-wafer (W2W). |
