Ouvrages publiés en collaboration (4)
  1. 1. Milojevic, D., Agrawal, P., Raghavan, P., Plas, G. V. D., Catthoor, F., & Beyne, E. (2019). Handbook of 3D Integration: Ultra-Fine Pitch 3D-Stacked Integrated Circuits: Technology, Design. doi:10.1002/9783527697052.ch2
  2. 2. Gogniat, G., Milojevic, D., Morawiec, A., & Erdogan, A. (2010). Algorithm-Architecture Matching for Signal and Image Processing: Best Papers from Design and Architectures for Signal and Image Processing 2007 & 2008 & 2009. Springer.
  3. 3. Milojevic, D., Leroy, A., Robert, F., Pierre, M. P., & Verkest, D. (2009). Networks-on-Chips: Theory and Practice: NoC-Based Implementation: MPSoC for Video Coding Applications.
  4. 4. Rupp, M., Milojevic, D., & Gogniat, G. (2008). Design and Architectures for Signal and Image Processing. Hindawi Publishing Corporation.
    5.   Ouvrages édités à titre de seul éditeur ou en collaboration (1)
  5. 1. Viviers, D., Milojevic, D., & Warzée, N. (2005). 3D Reconstruction of the Necropolis in Itanos, Crete: Proceedings of the 10th International Conference « Cultural Heritage and New Technologies. Vienne.
    6.   Parties d'ouvrages collectifs (2)
  6. 1. Doan, N. A. V., Milojevic, D., & De Smet, Y. (2016). MCDM applied to the partitioning problem of 3D-stacked integrated circuits. In Applications in Management and Engineering (pp. 165-187). Springer.
  7. 2. Milojevic, D., Varadarajan, R., Seynhaeve, D., & Marchal, P. (2011). Pathfinding and TechTuning. In Three Dimensional System Integration: IC Stacking Process and Design (pp. 137-185). Springer US. doi:10.1007/978-1-4419-0962-6_7
    8.   Articles dans des revues avec comité de lecture (40)
  8. 1. Delhaye, Q., Beyne, E., Goossens, J., Van Der Plas, G., & Milojevic, D. (2023). Impact of gate-level clustering on automated system partitioning of 3D-ICs. Microelectronics journal, 139, 105896. doi:10.1016/j.mejo.2023.105896
  9. 2. Sisto, G., Zografos, O., Chehab, B., Kakarla, N., Xiang, Y., Milojevic, D., Weckx, P., Hellings, G., & Ryckaert, J. (2022). Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era. IEEE transactions on very large scale integration (VLSI) systems, 30(10), 1497-1506. doi:10.1109/TVLSI.2022.3190080
  10. 3. Agnesina, A., Brunion, M., García-Ortiz, A., Catthoor, F., Milojevic, D., Komalan, M., Cavalcante, M., Riedel, S., Benini, L. L., & Lim, S. K. (2022). Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs. Proceedings - International Symposium on Low Power Electronics and Design., 15. doi:10.1145/3531437.3539702
  11. 4. Chen, R., Sisto, G., Stucchi, M., Jourdain, A., Miyaguchi, K., Schuddinck, P., Woeltgens, P., Lin, H., Kakarla, N., Veloso, A., Milojevic, D., Zografos, O., Weckx, P., Hellings, G., Van Der Plas, G., Ryckaert, J., & Beyne, E. (2022). Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node. Digest of technical papers - Symposium on VLSI Technology, 2022-June, 429-430. doi:10.1109/VLSITechnologyandCir46769.2022.9830328
  12. 5. Milojevic, D., Van Der Plas, G., & Beyne, E. (2022). Imec demonstrates significant performance gains utilizing backside 3D SOC interconnects. Semiconductor silicon, 43(1), 22-25.
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