Ouvrages publiés en collaboration (4)
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Milojevic, D., Agrawal, P., Raghavan, P., Plas, G. V. D., Catthoor, F., & Beyne, E. (2019). Handbook of 3D Integration: Ultra-Fine Pitch 3D-Stacked Integrated Circuits: Technology, Design. doi:https://doi.org/10.1002/9783527697052.ch2 Ouvrages édités à titre de seul éditeur ou en collaboration (1)
Parties d'ouvrages collectifs (2)
Articles dans des revues avec comité de lecture (40)
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Sisto, G., Zografos, O., Chehab, B., Kakarla, N., Xiang, Y., Milojevic, D., Weckx, P., Hellings, G., & Ryckaert, J. (2022). Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era. IEEE transactions on very large scale integration (VLSI) systems, 30(10), 1497-1506. doi:10.1109/TVLSI.2022.31900802.
Agnesina, A., Brunion, M., García-Ortiz, A., Catthoor, F., Milojevic, D., Komalan, M., Cavalcante, M., Riedel, S., Benini, L. L., & Lim, S. K. (2022). Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs. Proceedings - International Symposium on Low Power Electronics and Design., 15. doi:10.1145/3531437.35397023.
Chen, R., Sisto, G., Stucchi, M., Jourdain, A., Miyaguchi, K., Schuddinck, P., Woeltgens, P., Lin, H., Kakarla, N., Veloso, A., Milojevic, D., Zografos, O., Weckx, P., Hellings, G., Van Der Plas, G., Ryckaert, J., & Beyne, E. (2022). Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node. Digest of technical papers - Symposium on VLSI Technology, 2022-June, 429-430. doi:10.1109/VLSITechnologyandCir46769.2022.98303285.
Sisto, G., Chen, R., Chou, R., Van Der Plas, G., Beyne, E., Metcalfe, R., & Milojevic, D. (2021). Design and Sign-off Methodologies for Wafer-To-Wafer Bonded 3D-ICs at Advanced Nodes (invited). International Workshop on System Level Interconnect Prediction, SLIP, 2021-November, 17-23. doi:10.1109/SLIP52707.2021.00011