Articles dans des revues avec comité de lecture (41)
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Sisto, G., Chen, R., Chou, R., Van Der Plas, G., Beyne, E., Metcalfe, R., & Milojevic, D. (2021). Design and Sign-off Methodologies for Wafer-To-Wafer Bonded 3D-ICs at Advanced Nodes (invited). International Workshop on System Level Interconnect Prediction, SLIP, 2021-November, 17-23. doi:10.1109/SLIP52707.2021.000117.
Oprins, H., Milojevic, D., Van Der Plas, G., & Beyne, E. (2021). Thermal analysis of 3D functional partitioning for high-performance systems. InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITHERM, 2021-June, 145-153. doi:10.1109/ITherm51669.2021.95032098.
Beyne, E., Milojevic, D., Van Der Plas, G., & Beyer, G. (2021). 3D SoC integration, beyond 2.5D chiplets. Technical Digest - International Electron Devices Meeting, IEDM, 2021-December, 3.6.1-3.6.4. doi:10.1109/IEDM19574.2021.97206149.
Chen, R., Sisto, G., Jourdain, A., Hiblot, G., Stucchi, M., Kakarla, N., Chehab, B., Salahuddin, S. M., Schleicher, F., Veloso, A., Hellings, G., Weckx, P., Milojevic, D., Van Der Plas, G., Ryckaert, J., & Beyne, E. (2021). Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node. Technical Digest - International Electron Devices Meeting, IEDM, 2021-December, 22.4.1-22.4.4. doi:10.1109/IEDM19574.2021.972052811.
Agnesina, A., Brunion, M., Kim, J., García-Ortiz, A., Milojevic, D., Catthoor, F., Perumkunnil, M., & Lim, S. K. (2021). Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs. Proceedings - International Symposium on Low Power Electronics and Design, 2021-July, 9502475. doi:10.1109/ISLPED52811.2021.950247512.
Zhu, L., Bamberg, L., Pentapati, S. S. K., Chang, K., Catthoor, F., Milojevic, D., Komalan, M., Cline, B., Sinha, S., Xu, X., García-Ortiz, A., & Lim, S. K. (2021). High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors. IEEE transactions on very large scale integration (VLSI) systems, 29(6), 9420273, 1152-1163. doi:10.1109/TVLSI.2021.307307013.
Sharma, G., Bousdras, G., Ellinidou, S., Markowitch, O., Dricot, J.-M., & Milojevic, D. (2021). Exploring the security landscape: NoC-based MPSoC to Cloud-of-Chips. Microprocessors and microsystems, 103963. doi:10.1016/j.micpro.2021.10396314.
Chen, R., Weckx, P., Salahuddin, S. M., Kim, S.-W., Sisto, G., Van Der Plas, G., Stucchi, M., Baert, R., Debacker, P., Na, M.-H., Ryckaert, J., Milojevic, D., & Beyne, E. (2020). 3D-optimized SRAM macro design and application to memory-on-logic 3D-IC at advanced nodes. Technical Digest - International Electron Devices Meeting, IEDM, 2020-December, 9371905, 15.2.1-15.2.4. doi:10.1109/IEDM13553.2020.937190515.
Perumkunnil, M., Yasin, F., Rao, S., Salahuddin, S. M., Milojevic, D., Van Der Plas, G., Ryckaert, J., Beyne, E., Furnemont, A., & Kar, G. S. (2020). System exploration and technology demonstration of 3D Wafer-to-Wafer integrated STT-MRAM based caches for advanced Mobile SoCs. Technical Digest - International Electron Devices Meeting, IEDM, 2020-December, 9372046, 15.4.1-15.4.4. doi:10.1109/IEDM13553.2020.937204616.
Milojevic, D., Beyne, E., Van Der Plas, G., Wang, J. J., & Debacker, P. (2020). Cost-performance optimization of fine-pitch W2W bonding: Functional system partitioning with heterogeneous FEOL/BEOL configurations. Proceedings of SPIE - The International Society for Optical Engineering, 11328, 113280R. doi:10.1117/12.255203617.
Zhu, L., Bamberg, L., Agnesina, A., Catthoor, F., Milojevic, D., Komalan, M., Ryckaert, J., García-Ortiz, A., & Lim, S. K. (2020). Heterogeneous 3D Integration for a RISC-V System with STT-MRAM. I E E E Computer Architecture Letters, 19(1), 9086777, 51-54. doi:10.1109/LCA.2020.2992644