Communications publiées lors de congrès ou colloques nationaux et internationaux (66)
  1. 1. Potvin, N., Bersini, H., & Milojevic, D. (2022). Espresso to the rescue of genetic programming facing exponential complexity. GECCO 2022 Companion - Proceedings of the 2022 Genetic and Evolutionary Computation Conference (p. 590–593). doi:https://doi.org/10.1145/3520304.3529005
  2. 2. Calvacante, M., Agnesina, A., Riedel, S., Brunion, M., García-Ortiz, A., Milojevic, D., Catthoor, F., Lim, S. K., & Benini, L. L. (2022). MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration. Proceedings of the 2022 (pp. 394-399) Design, Automation and Test in Europe Conference and Exhibition, DATE 2022.
  3. 3. Sisto, G., Chehab, B., Genneret, B., Rogier, B., Chen, R., Weckx, P., Ryckaert, J., Chou, R., Plas, G. V. D., Beyne, E., & Milojevic, D. (2021). IR-Drop Analysis of Hybrid Bonded 3D-ICs with Backside Power Delivery and μ-& N-TSVssi. 2021 IEEE International Interconnect Technology Conference (IITC) (2021-09-20) doi:10.1109/IITC51362.2021.9537541
  4. 4. Sisto, G., Debacker, P., Ron, C. R., Van der Plas, G., Beyne, E., Richard, C. R., & Milojevic, D. (2020). Design enablement of fine pitch face-to-face 3D system integration using die-by-die place & route. IEEE 2019 International 3D Systems Integration Conference (2019-10-08) doi:10.1109/3DIC48104.2019.9058901
  5. 5. Milojevic, D., Beyne, E., Plas, G. V. D., Wang, J. J., & Debacker, P. (2020). Cost-performance optimisation of fine-pitch W2W bonding: functional system partitioning with heterogeneous FEOL/BEOL configurations. SPIE Advanced Lithography (2020-02-20: San Jose, USA)
  6. 6. Delhaye, Q., Milojevic, D., & Goossens, J. (2019). 3D-Stacked Integrated Circuits: How Fine Should System Partitioning Be? Proceedings - IEEE International Symposium on Circuits and Systems IEEE International Symposium on Circuits and Systems(2019: 26-29 May 2019: Sapporo, Japan) doi:10.1109/ISCAS.2019.8702533
  7. 7. Bousdras, G., Quitin, F., & Milojevic, D. (2018). Template architectures for highly scalable, many-core Heterogeneous SoC: Could-of-Chips. 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) doi:10.1109/ReCoSoC.2018.8449383
  8. 8. Luca, M., Gerousis, V., & Milojevic, D. (2018). Efficient place and route enablement of 5-tracks standard- cells through EUV compatible N5 ruleset. Design-Process-Technology Co-optimization for Manufacturability doi:10.1117/12.2297336
  9. 9. Luca, M., Debacker, P., & Milojevic, D. (2017). IR-drop aware Design & Technology Co-Optimization for N5 node with different device and cell height options. ICCAD Conference ICCAD doi:10.1109/ICCAD.2017.8203764
  10. 10. Milojevic, D. (2017). Library-level characterization of sub-10nm processing nodes. CDNLive EMEA CDNLive Conference
  11. 11. Ku, B. W., Debacker, P., Milojevic, D., Raghavan, P., & Lim, S. K. (2017). How Much Cost Reduction Justifies the Adoption of Monolithic 3D ICs at 7Nm Node? In Proceedings of the 35th International Conference on Computer-Aided Design (pp. 87:1-87:7). (ICCAD '16). ACM. doi:10.1145/2966986.2967044
  12. 12. Allard, Y., Milojevic, D., & Goossens, J. (2017). Can we get a predictable cache system for real-time computer systems? Heterogeneous Architectures and Real-Time Systems
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