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Heterogeneous 3D Integration for a RISC-V System with STT-MRAM

par Zhu, Lingjun;Bamberg, Lennart;Agnesina, Anthony;Catthoor, Francky;Milojevic, Dragomir ;Komalan, Manu;Ryckaert, Julien;García-Ortiz, Alberto;Lim, Sung Kyu
Référence I E E E Computer Architecture Letters, 19, 1, page (51-54), 9086777
Publication Publié, 2020-01-01

Article révisé par les pairs

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Résumé :

Spin Torque Transfer Magnetic RAM (STT-MRAM) is a promising Non-Volatile Memory (NVM) technology achieving high density, low leakage power, and relatively small read/write delays. It provides a solution to improve the performance and to mitigate the leakage power consumption compared to SRAM-based processors. However, the process heterogeneity and the sophisticated back-end-of-line (BEOL) structure make it difficult to integrate the STT-MRAM in two-dimensional integrated circuits (2D ICs). In this article, we implement a RISC-V-based processor with STT-MRAM using a heterogeneous 3D integration methodology. Compared with the SRAM-based 2D counterpart, the MRAM-based 3D IC provides up to 17.55 percent silicon area saving, together with either 34.74 percent performance gain or 13.90 percent energy reduction.