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Handbook of 3D Integration: Ultra-Fine Pitch 3D-Stacked Integrated Circuits: Technology, Design

par Milojevic, Dragomir ;Agrawal, Prashant;Raghavan, Praveen;Plas, Geert Van der;Catthoor, Francky;Beyne, Eric
Référence Vol. 4, Ed. 1
Publication Publié, 2019-02-08

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Résumé :

Today through‐silicon via (TSV) is a mature process technology option for manufacturing of 3D stacked integrated circuits (3D‐SIC). This chapter shows the results of the system‐level/process technology co‐design analysis. It presents a design flow for carrying out exploration of 2D and 3D‐SIC implementations. The chapter considers multiple variations of a complex mobile MPSoC platform instantiated for real‐life streaming wireless applications. It focuses on Cu‐Cu bonding‐based face‐to‐face (F2F) stacking in the case of 3D‐SIC implementations because it carries out fine‐grained memory‐on‐logic 3D partitioning, resulting in 2‐layer 3D‐SIC implementations with very large number of inter‐die connections. It uses the following three factors to broadly classify different technology options: (i) integration granularity, (ii) stacking orientation, and (iii) TSV formation. The chapter presents a a case study where it explores 2D and 3D‐SIC implementations for mobile MPSoC platform targeted at wireless baseband processing. It also considers ultrafine pitch 3D interconnections using Cu‐Cu pad bonding and F2F stacking.