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Design enablement and system level characterization of sub-2nm CMOS technology nodes and 3D multi-die package integration

par Naeim, Mohamed
Président du jury Dricot, Jean-Michel
Promoteur Milojevic, Dragomir
Publication Non publié, 2025-08-28

Thèse de doctorat

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Résumé :

Denser CMOS technologies have been a catalyst for continuous miniaturization, drivinglarge volumes at low cost and enabling unprecedented system-level innovations. Technologyscaling across logic, memory, and 3D integration enables higher compute, memory,bandwidth density and is a key factor towards scalable system design. In the "Morethan Moore" era, System-Technology Co-Optimization (STCO) emerges as a promisingparadigm to harness the synergy between new technologies and application-driven architectures, achieving higher efficiency and performance while maintaining cost parity. STCO aims to co-optimize various aspects of chip design, starting from architecturalenhancements, workload selection, and tuning technology parameters such as 3D integration. In this thesis, we demonstrate the benefits of 3D integration as an alternativeto device scaling, which sustains Moore’s law. We explore two design architectures that address two prominent application domains: systolic array for Artificial Intelligence (AI) inferences and general-purpose many-core architecture. The Place and Route (PNR) results of systolic array design show that 3D Memory-on-Logic (MoL) partitioning scheme saves 8% of total power at iso-frequency, compared to the 2D baseline implementation. Combined with 3D integration, Magnetic Random Access Memory (MRAM)-based Non-Volatile Memory (NVM) is proposed as a candidate for on-chip usage, offering advantagesin footprint and leakage power reduction. Integrating NVM macros instead of SRAM macros in the 3D implementation allows 4× memory capacity increase with 30% footprint reduction compared to the baseline design with SRAM. We show that, withinthe context of STCO, multiple parameters need to be adjusted to achieve clear Power, Performanceand Area (PPA) benefits. These include technology parameters such as 3D-IC with different partitioning scenarios and emerging memory devices, as well as architectural and workload parameters that are intertwined to achieve optimal performance for a given workload. However, the miniaturization and footprint reduction in 3D-IC haveled to power density becoming a bottleneck that needs to be addressed. To tackle this,thermal analysis is conducted for different 3D bonding technologies (e.g. Wafer-to-WaferHybrid Bonding (W2W-HB) and Embedded micro-Bumps (E-μBumps)), each with distinct technology parameters affecting their thermal behavior. The study demonstrates that, MoL configuration exhibits higher temperature, 5C above the 2D baseline, while 3-tier stack increase temperature by 12C , necessitating more powerful cooling system with extra 33% heat transfer efficiency to reduce maximum temperature. Additionally, the Frontside PDN (FS-PDN) is compared with the Backside PDN (BS-PDN) for thermal analysis. Compared to FS-PDN, introducing BS-PDN results in 2C increase for 2Dand 2C reduction for 3D MoL configuration. After understanding the thermal challenges in 3D-IC and strategies to mitigate the expected temperature rise in 3D and BS-PDN, it is essential to perform electrical-thermal co-simulation analysis. This analysis provides accurate calculations for various metrics such as power, interconnect resistance, and IRdrop. A framework has been developed on top of existing Electronic Design Automation (EDA) tools to bridge the gap between electrical and thermal domains, identifying thermal runaway and thermal stability conditions for a chip. This framework demonstrates that an increase in temperature leads to a corresponding increase in power, which in turn causes further temperature rise, creating a feedback loop. Results indicate that the power and temperature values reported in the first iteration cannot be trusted as they increase with each iteration. For example, total power and hence temperature values increase by 21% and +6C , respectively, from iteration 1 until reaching stability. This thesis aims to utilize STCO in combination with 3D integration to demonstrate potential gains at advanced technology nodes below 2nm, while addressing associated challenges such as thermal and power density barriers.