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Automated System Partitioning for Efficient 3D Circuit Integration

par Delhaye, Quentin
Président du jury Mühlberg, Jan Tobias
Promoteur Milojevic, Dragomir
Co-Promoteur Goossens, Joël
Publication Non publié, 2024-03-04

Thèse de doctorat

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Résumé :

A Venn diagram comparing a computer, a car, an industrial robot and smart toaster would point to one piece of technology: the integrated circuit, or IC. Since the mid-20th century, it has grown omnipresent, evermore integrated and denser. The consumers' demand and industry relentless drive for more performance pushes the traditional technology to its last ditch. A short to mid-term solution to keep the trend going would be to stack layers of components, turning the IC 3D.If there are several tiers where elements are placed, one should take a decision regarding which component will occupy which layer, an endeavour regarded as a partitioning problem. It can be tackled by hand, but the size and complexity of modern systems require an automated approach so that the resulting partitions can be generated in accordance with optimisation objectives that tend to produce efficient results. This leads to automated system partitioning for efficient 3D circuit integration.Even though the problem has been studied for the past couple of decades, there is still a lot of open wondering: What is the grain at which we should consider the partitioning decision; should we consider each component individually or group them somehow beforehand? What is a good 3D partition and how does the hypergraph representation of the circuit impact its quality? How can we efficiently leverage information from a regular 2D circuit to take a partitioning decision? Is there an established advantage to automatically partition a system compare to a manual operation?To tackle those problems and achieve an automated system partitioning, we studied and developed a suite of methods that ingests a 2D description of a circuit and produces a 3D representation that can be further processed into a functional 3D IC.The proposed methodology leverages the information of a 2D placement by (1) extracting the design and its interconnectivity, (2) clustering the circuit to keep elements together as we deem more beneficial, (3) representing the system as a hypergraph and properly partition it according to optimisation objectives, and (4) generating files that represent our 3D circuit in such a fashion that it can be understood by other tools.This proposed partitioning flow supported a series of experiments to bring some answers to the various questions surrounding the field.Specifically, we showed that (1) there is an advantage to approaching a partitioning problem from a block-level rather than a gate-level perspective. In particular for benchmarked designs between 40k and 800k standard cells, with either local or global dominated interconnect, and with memory macros accounting for less than half the floorplan area or none at all, it appeared that around 2,000 geometric clusters was a sweet spot regarding the amount of wires cut and the total system wire-length they represent.Furthermore, we highlighted that (2) the choice of the clustering method applied before partitioning the system can have a significant impact on the partitioning quality and thus on the resulting 3D system performance, with up to 7% higher effective frequency compared to applying no clustering, and 4% better than the second best method tested.Finally, we studied that (3) automatically partitioning a circuit with large memory macros and templated cores has a tendency to keep each functional unit packed on the same die, similar to what a human might do manually, even if the partitioning is applied on a flattened gate-level netlist.