par Clerbaux, Barbara ;Colomer Molla, Marta ;Petitjean, Pierre-Alexandre ;Xu, Yu;Yifan, Yang
Référence IEEE transactions on nuclear science, 68, 8, page (2187-2193), 9445104
Publication Publié, 2021-08-01
Référence IEEE transactions on nuclear science, 68, 8, page (2187-2193), 9445104
Publication Publié, 2021-08-01
Article révisé par les pairs
Résumé : | A study on the use of a machine learning algorithm for the level 1 trigger decision in the Jiangmen Underground Neutrino Observatory (JUNO) experiment is presented. JUNO is a medium baseline neutrino experiment under construction in China, with the main goal of determining the neutrino mass hierarchy. A large liquid scintillator (LS) volume will detect the electron antineutrinos issued from nuclear reactors. The LS detector is instrumented by around 20 000 large photomultiplier tubes (PMTs). The hit information from each PMT will be collected into a central trigger unit for the level 1 trigger decision. The current trigger algorithm used to select a neutrino signal event is based on a fast vertex reconstruction. We propose to study an alternative level 1 (L1) trigger in order to achieve a similar performance as the vertex fitting trigger but with fewer logic resources by using a firmware implemented machine learning model at the L1 trigger level. We treat the trigger decision as a classification problem and train a multilayer perceptron (MLP) model to distinguish the signal events with energy higher than a certain threshold from noise events. We use JUNO software to generate datasets that include 100k physics events with noise and 100k pure noise events coming from PMT dark noise. For events with energy higher than 100 keV, the L1 trigger based on the converged MLP model can achieve an efficiency of higher than 99%. After the training performed on simulations, we successfully implemented the trained model into a Kintex 7 field-programmable gate array (FPGA). We present the technical details of the neural network development and training, as well as its implementation in the hardware with the FPGA programming. Finally, the performance of the L1 trigger MLP implementation is discussed. |