par Delhaye, Quentin 
;Milojevic, Dragomir ;Goossens, Joël
Référence IEEE International Symposium on Circuits and Systems(2019: 26-29 May 2019: Sapporo, Japan), Proceedings - IEEE International Symposium on Circuits and Systems
Publication Publié, 2019-05-26
;Milojevic, Dragomir ;Goossens, Joël Référence IEEE International Symposium on Circuits and Systems(2019: 26-29 May 2019: Sapporo, Japan), Proceedings - IEEE International Symposium on Circuits and Systems
Publication Publié, 2019-05-26
Publication dans des actes
| Résumé : | 3D stacked ICs package multiple, independently manufactured dies to reduce total system wire-length, improve timing, and reduce area and power. When designing stacked 3D-ICs, arises the question of the grain at which one should consider system partitioning to optimize the gains. This work uses known MAX-CUT graph partitioning algorithms to split designs from 42k up to 800k gates, with gates clustered from 8 and up to 32768 partitions. It has been found that with 2048 clusters, i.e. 20 to 400 gates per cluster depending on the design, a partitioning of the system allows on average to cut 35% of the nets that account for 73% of the total wire-length in 3D. |
