par Lambrechts, Andy;Raghavan, Praveen;Leroy, Anthony 
;Talavera, Guillermo G.;Vander Aa, Tom;Jayapala, Murali M.;Catthoor, Francky;Verkest, Diederik D.;Deconinck, Geert G.;Corporaal, Henk H.;Robert, Frédéric ;Carrabina, Jordi
Référence Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors, page (179-184)
Publication Publié, 2005
;Talavera, Guillermo G.;Vander Aa, Tom;Jayapala, Murali M.;Catthoor, Francky;Verkest, Diederik D.;Deconinck, Geert G.;Corporaal, Henk H.;Robert, Frédéric ;Carrabina, JordiRéférence Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors, page (179-184)
Publication Publié, 2005
Article révisé par les pairs
| Résumé : | Users expectifuture handheld devices to provide extended multimedia functionality and have long battery life. This type of application imposes heavy constraints on performance and power consumption and forces designers to optimize all parts of their platform. Evaluating the overall platform power breakdown is therefore critical to determine where to spend the efforts on power optimization. Surprisingly, few studies exist on that topic and decisions generally rely on common belief. We have realized a complete power breakdown for a realistic platform to identify the major power bottlenecks. This paper presents this power assessment of a realistic heterogeneous network on chip platform including processors, network and data/instruction memory hierarchy, running a video processing chain from camera to display. Our power breakdown identifies the main bottle-necks in the memory hierarchy and the foreground memory, and shows that global interconnect is not that critical for a well-optimizediapplication mapping. © 2005 IEEE. |
